1. Field of the Invention
The present invention generally relates to memory controllers. More specifically, the invention relates to memory controllers operating in a system with a variable system clock.
2. Description of the Related Art
A system on a chip (SOC) generally includes one or more integrated processor cores, some type of embedded memory, such as a cache shared between the processor cores, and peripheral interfaces, such as memory control components and external bus interfaces, on a single chip to form a complete (or nearly complete) system. The external bus interface is often used to pass data in packets over an external bus between the SOC and an external device, such as an external memory controller.
The increasing demand for higher processor performance has lead to dramatic increases in clock frequencies of processor cores. As the chips become faster and larger, improving performance while containing power dissipation has become a significant challenge. One solution to conserve power may be to implement multiple clock domains in the processor. A Multiple Clock Domain (MCD) processor may comprise one or more clock domains that run at different frequencies. Moreover, the voltage and frequency for each domain may be independently and dynamically controlled, thereby allowing the selection of frequencies and voltages that conserve energy and maximize performance.
One challenge in implementing such a solution is that memory interfaces typically require a constant frequency. Therefore, the memory controller must be able to accommodate frequency changes in the processor core. For example, the memory controller may contain large command queues to receive read and write commands from the processor in the processor clock domain. The memory controller may also contain memory interface sequencers in the memory clock domain. The memory interface sequencers, for example, may be configured to perform memory accesses such as read and write accesses at a constant frequency in the memory clock domain.
The memory controller may also contain asynchronous read and write buffers configured to exchange data between the different clock domains. For example an asynchronous read buffer may be configured to receive read data from memory in the memory clock domain and send the read data to the processor in the processor clock domain. Similarly, an asynchronous write buffer may receive write data from the processor in the processor clock domain and send the write data to memory in the memory clock domain.
One problem with this solution is that if the frequency of the processor core changes, the buffers may overflow in some instances and under run in other instances. For example, if the processor frequency is reduced with respect to the memory frequency to conserve power, read data from memory may be received in the read buffer at a rate greater than the rate at which the data is read by the processor from the buffer. Therefore, the read buffer may overflow.
On the other hand, with respect to the write buffers, if the processor frequency is slowed relative to the memory frequency, a write buffer under run may occur. For example, write data in the write buffers may be transferred to memory based on assumptions regarding the availability of data in the write buffer. The assumptions, for example, may include the timing for transfer of data from the processor to the write buffer. If the processor frequency is reduced, write data may be transferred to the write buffers at a slower rate, thereby invalidating previous assumptions. In other words, data may not be written fast enough to satisfy timing requirements of the memory device.
Therefore, what is needed are methods and systems for allowing memory controllers to accommodate frequency changes in processors.